ISP1362
Single-chip USB OTG controller
Philips Semiconductors
11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
address lines in three-state and deasserts the HRQ signal, informing the CPU
that it has released the bus.
12. The CPU acknowledges control of the bus by deasserting HLDA. After activating
the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the
CPU resumes the execution of instructions.
For a typical bulk transfer, the preceding process is repeated 32 times, once for each
word. After each word, the DcAddress register in the DMA controller is incremented
by two and the byte counter is decremented by two. When using the 16-bit DMA, the
number of transfers is 32 and address incrementing and byte counter decrementing
is done by two for each word.
13.4.3 End-Of-Transfer conditions
Bulk endpoints: A DMA transfer to or from a bulk endpoint can be terminated by any
of the following conditions (bit names refer to the DcDMAConfiguration register, see
Table 118 and Table 119):
• The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
• A short packet is received on an enabled OUT endpoint (SHORTP = 1)
• DMA operation is disabled by clearing the DMAEN bit.
DcDMACounter register — An EOT from the DcDMACounter register is enabled by
setting bit CNTREN of the DcDMAConfiguration register. The DC has a 16-bit
DcDMACounter register, which specifies the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA
operation stops.
Short packet — Normally, the transfer byte count must be set using a control
endpoint before any DMA transfer takes place. When a short packet has been
enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the
presence of a short packet in the data. This mechanism permits the use of a fully
autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token
will stop the DMA operation after transferring the data bytes of this packet.
Table 19: Summary of EOT conditions for a bulk endpoint
EOT condition
OUT endpoint
IN endpoint
DcDMACounter register
transfer completes as
programmed in the
transfer completes as
programmed in the
DcDMACounter register
DcDMACounter register
Short packet
short packet is received and
transferred
counter reaches zero in
the middle of the buffer
DMAEN bit of the
DMAEN = 0[1]
DMAEN = 0[1]
DcDMAConfiguration register
[1] The DMA transfer stops. No interrupt, however, is generated.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
57 of 150
NXP [ NXP ]
