ISP1362
Single-chip USB OTG controller
Philips Semiconductors
20.2.2 HC burst mode DMA timing
Table 154: Dynamic characteristics: HC burst mode DMA timing
Symbol Parameter Conditions
Read/write timing (for 4-cycle and 8-cycle burst mode)
Min
Typ
Max
Unit
tRL
WR/RD LOW pulse width
WR/RD HIGH to next WR/RD LOW
WR/RD cycle
42
60
102
22
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRHRL
TRC
-
-
tSLRL
tSHAH
tRHAL
TDC
RD/WR LOW to DREQ1 LOW
RD/WR HIGH to DACK1 HIGH
DREQ1 HIGH to DACK1 LOW
DREQ1 cycle
64
-
0
[1]
-
-
-
-
-
tDS(read) DREQ1 pulse spacing (read)
4-cycle burst mode
8-cycle burst mode
4-cycle burst mode
8-cycle burst mode
105
150
72
tDS(write) DREQ1 pulse spacing (write)
167
[1] tSLAL + (4 or 8)tRC + tDS
t
DS
DREQ1
t
t
RHSH
SLRL
t
RHAL
DACK1
t
t
SHAH
RHRL
RD or WR
004aaa108
T
RC
t
RLRH
Fig 34. HC burst mode DMA timing.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
139 of 150
NXP [ NXP ]
