ISP1362
Single-chip USB OTG controller
Philips Semiconductors
t
t
RHAX
A0
t
AVRL
SHDZ
CS/DACK2(2)
(1)
t
t
SHRL
RLRH
RD
t
RHSH
t
RLDV
D[15:0]
004aaa105
(1) For tSHRL both CS and RD must be deasserted.
(2) Programmable polarity: shown as active LOW.
Fig 31. DC Programmed interface read timing (I/O and 8237 compatible DMA).
t
WHAX
A0
t
AVWL
CS/DACK2(2)
t
WLWH
(1)
t
SHWL
t
WHSH
WR
t
t
DVWH
WHDZ
D[15:0]
004aaa106
(1) For tSHWL both CS and WR must be deasserted.
(2) Programmable polarity: shown as active LOW.
Fig 32. DC Programmed interface write timing (I/O and 8237 compatible DMA).
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
137 of 150
NXP [ NXP ]
