ISP1362
Single-chip USB OTG controller
Philips Semiconductors
CS
A0
t
t
SLRL
SLWL
t
SHSL
t
RLRH
t
t
WHSH
RHSH
t
RHRL
T
RC
RD
t
RLDV
t
RHDZ
[
]
D 15:0
data
valid
data
valid
data
valid
data
valid
t
AS
t
WHWL
t
t
T
WC
AH
WL
WR
t
t
WDH
WDSU
data
valid
data
valid
data
valid
data
valid
data
valid
[
]
D 15:0
MGT969
Fig 30. HC Programmed interface timing.
20.1.2 DC Programmed I/O timing
Table 152: Dynamic characteristics: DC Programmed interface timing
Symbol Parameter Conditions
Read timing (see Figure 31)
Min
Typ
Max
Unit
tRHAX
tAVRL
tSHDZ
address hold time after RD HIGH
3
0
-
-
-
-
-
ns
ns
ns
address set-up time before RD LOW
-
data outputs high-impedance time after
CS HIGH
3
tRHSH
chip deselect time after RD HIGH
RD pulse width
0
-
-
-
-
-
ns
ns
ns
ns
tRLRH
25
-
-
tRLDV
data valid time after RD LOW
read cycle time
22
-
tSHRL + tRLRH + tRHSH
180
Write timing (see Figure 32)
tWHAX address hold time after WR HIGH
tAVWL address set-up time before WR LOW
tSHWL + tWLWH + tWHSH write cycle time
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
0
[1]
180
22
0
tWLWH
tWHSH
tDVWH
tWHDZ
WR pulse width
chip deselect time after WR HIGH
data set-up time before WR HIGH
data hold time after WR HIGH
5
3
[1] In the command to data phase, the minimum value of the write command to the read data or write data cycle time should be 205 ns.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
136 of 150
NXP [ NXP ]
