ISP1362
Single-chip USB OTG controller
Philips Semiconductors
20.2.5 DC single-cycle DMA write timing in DACK-only mode
Table 157: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode
Symbol
tASRP
Parameter
Conditions
Min
Typ
Max
40
-
Unit
ns
DREQ2 off after DACK2 on
DACK2 pulse width
-
-
-
-
-
-
tASAP
25
ns
tASAP + tAPRS DREQ2 on after DACK2 off
180
-
ns
tASDV
tAPDZ
data valid after DACK2 on
data hold after DACK2 off
-
-
22
3
ns
ns
t
ASAP
t
t
APRS
ASRP
DREQ2
t
t
ASDV
APDZ
(1)
DACK2
DATA
004aaa113
(1) Programmable polarity: shown as active LOW.
Fig 37. DC single-cycle DMA write timing in DACK-only mode.
20.2.6 DC burst mode DMA timing
Table 158: Dynamic characteristics: DC burst mode DMA timing
Symbol
tRSIH
tILRP
Parameter
Conditions
Min
22
-
Typ
Max
Unit
ns
input RD/WR HIGH after DREQ on
DREQ off after input RD/WR LOW
DACK off after input RD/WR HIGH
-
-
-
-
-
-
ns
tIHAP
0
60
-
ns
tIHIL
DMA burst repeat interval (input
RD/WR HIGH to LOW)
tRL or tWL is 30 ns (min)
160
ns
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
141 of 150
NXP [ NXP ]
