ISP1362
Single-chip USB OTG controller
Philips Semiconductors
20.2 DMA timing
20.2.1 HC single-cycle DMA timing
Table 153: Dynamic characteristics: HC single-cycle DMA timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Read/write timing
tRL
RD pulse width
33
30
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRLDV
tRHDZ
tWSU
tWHD
tAHRH
tALRL
TDC
read process data set-up time
read process data hold time
write process data set-up time
write process data hold time
DACK1 HIGH to DREQ1 HIGH
DACK1 LOW to DREQ1 LOW
DREQ1 cycle
-
-
5
-
0
-
72
-
-
21
-
[1]
tSHAH
tRHAL
tDS
RD/WR HIGH to DACK1 HIGH
DREQ1 HIGH to DACK1 LOW
DREQ1 pulse spacing
0
-
0
-
146
-
[1] tRHAL + tDS +tALRL
T
DC
DREQ1
DACK1
t
DS
t
ALRL
t
SHAH
t
RHAL
t
AHRH
t
t
RHDZ
RLDV
[
]
]
D 15:0
data
valid
(read)
[
D 15:0
data
valid
(write)
t
WSU
RD or WR
004aaa107
t
WHD
Fig 33. HC single-cycle DMA timing.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
138 of 150
NXP [ NXP ]
