ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 113: DcMode register: bit description
Bit
7 to 6
5
Symbol
-
Description
reserved
GOSUSP
Writing logic 1 followed by logic 0 will activate the ‘suspend’
mode.
4
3
2
-
reserved
INTENA
DBGMOD
Logic 1 enables all interrupts. Bus reset value: unchanged.
Logic 1 enables debug mode, in which all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, in which
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
1
0
-
reserved
SOFTCT
Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1
in the DcHardwareConfiguration register (see Table 114). Bus
reset value: unchanged.
Remark: In the OTG mode, this bit is ignored. The LOC_CONN
bit of the OtgControl register controls the pull-up resistor on the
OTG_DP1 pin.
16.1.4 DcHardwareConfiguration register (R/W: BBH/BAH)
This command is used to access the DcHardwareConfiguration register, which
consists of two bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in Table 114. A bus reset will not change any
of the programmed bit values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during the ‘suspend’ state, as well as output clock
frequency, DMA operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write or read DcHardwareConfiguration register
Transaction — write or read 2 bytes (code or data)
Table 114: DcHardwareConfiguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
EXTPUL
NOLAZY
CLKRUN
CKDIV[3:0]
-
0
R/W
6
1
R/W
5
0
0
0
1
R/W
1
1
R/W
0
-
R/W
R/W
R/W
7
DAKOLY
0
4
3
WKUPCS
0
2
reserved
1
Symbol
Reset
Access
DRQPOL
1
DAKPOL
0
reserved
INTLVL
0
INTPOL
0
0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
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