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ISP1362BD 参数 Datasheet PDF下载

ISP1362BD图片预览
型号: ISP1362BD
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片通用串行总线- The-Go的控制器 [Single-chip Universal Serial Bus On-The-Go controller]
分类和应用: 控制器
文件页数/大小: 150 页 / 621 K
品牌: NXP [ NXP ]
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ISP1362  
Single-chip USB OTG controller  
Philips Semiconductors  
16.1.2 DcAddress register (R/W: B7H/B6H)  
This command is used to set the USB assigned address in the DcAddress register  
and enable the USB device. The DcAddress register bit allocation is shown in  
Table 110.  
A USB bus reset sets the device address to 00H (internally) and enables the device.  
The value of the DcAddress register (accessible by the microprocessor) is not altered  
by the bus reset. In response to the standard USB request Set Address, the rmware  
must issue a Write Device Address command, followed by sending an empty packet  
to the host. The new device address is activated when the host acknowledges the  
empty packet.  
Code (Hex): B6/B7 write or read DcAddress register  
Transaction write or read 1 byte (code or data)  
Table 110: DcAddress register: bit allocation  
Bit  
7
DEVEN  
0
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
DEVADR[6:0]  
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 111: DcAddress register: bit description  
Bit  
7
Symbol  
Description  
DEVEN  
Logic 1 enables the device.  
6 to 0  
DEVADR[6:0] This eld species the USB device address.  
16.1.3 DcMode register (R/W: B9H/B8H)  
This command is used to access the DcMode register, which consists of 1 byte (bit  
allocation: see Table 112). In the 16-bit bus mode, the upper byte is ignored.  
The DcMode register controls the DMA bus width, the resume and suspend modes,  
interrupt activity, and SoftConnect operation. It can be used to enable the debug  
mode, in which all errors and Not Acknowledge (NAK) conditions will generate an  
interrupt.  
Code (Hex): B8/B9 write or read DcMode register  
Transaction write or read 1 byte (code or data)  
Table 112: DcMode register: bit allocation  
Bit  
7
6
5
GOSUSP  
0
4
reserved  
0
3
INTENA  
0[1]  
2
DBGMOD  
0[1]  
1
reserved  
0[1]  
0
SOFTCT  
0[1]  
Symbol  
Reset  
Access  
reserved  
1[1]  
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
[1] Unchanged by a bus reset.  
9397 750 12337  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 06 January 2004  
114 of 150  
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