ISP1362
Single-chip USB OTG controller
Philips Semiconductors
16.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of the DC and to
perform a device reset.
16.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH)
This command is used to access the DcEndpointConfiguration register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint
buffer memory. The register bit allocation is shown in Table 108. A bus reset will
disable all endpoints.
The allocation of buffer memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and must be configured with their default values (see Table 14). Automatic
buffer memory allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the buffer memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 108: DcEndpointConfiguration register: bit allocation
Bit
7
FIFOEN
0
6
EPDIR
0
5
DBLBUF
0
4
FFOISO
0
3
2
1
0
Symbol
Reset
Access
FFOSZ[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 109: DcEndpointConfiguration register: bit description
Bit
Symbol
Description
7
FIFOEN
Logic 1 indicates an enabled buffer memory with allocated
memory. Logic 0 indicates a disabled buffer memory (no bytes
allocated).
6
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
5
4
DBLBUF
FFOISO
Logic 1 indicates that this endpoint has double buffering.
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a
bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the buffer memory size according to Table 15.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
113 of 150
NXP [ NXP ]
