ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 118: DcDMAConfiguration register: bit allocation
Bit
15
CNTREN
0[1]
14
SHORTP
0[1]
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
6
-
7
5
4
3
2
1
0
Symbol
Reset
Access
EPDIX[3:0]
DMAEN
0
reserved
BURSTL[1:0]
0[1]
0[1]
0[1]
0[1]
-
-
0[1]
0[1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1] Unchanged by a bus reset.
Table 119: DcDMAConfiguration register: bit description
Bit
Symbol
Description
15
CNTREN
Logic 1 enables the generation of an EOT condition, when the
DcDMACounter register reaches zero. Bus reset value:
unchanged.
14
SHORTP
Logic 1 enables the short or empty packet mode. When
receiving (OUT endpoint) a short or empty packet, an EOT
condition is generated. When transmitting (IN endpoint), this bit
should be cleared. Bus reset value: unchanged.
13 to 8
7 to 4
3
-
reserved
EPDIX[3:0]
DMAEN
Indicates the destination endpoint for DMA, see Table 17.
Writing logic 1 enables DMA transfer, logic 0 forces the end of
an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped; 1 = DMA enabled). This bit
is cleared by a bus reset.
2
-
reserved
1 to 0
BURSTL[1:0] Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
16.1.7 DcDMACounter register (R/W: F3H/F2H)
This command accesses the DcDMACounter register, which consists of two bytes.
The bit allocation is given in Table 120. Writing to the register sets the number of
bytes for a DMA transfer. Reading the register returns the number of remaining bytes
in the current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register
when DMA is re-enabled (DMAEN = 1). See Section 16.1.6 for more details.
Code (Hex): F2/F3 — write or read DcDMACounter register
Transaction — write or read 2 bytes (code or data)
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
118 of 150
NXP [ NXP ]
