ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 107: DC command and register summary…continued
Name
Destination
Code (Hex)
Transaction[1]
Read Endpoint n Status
(n = 1 to 14)
DcEndpointStatus register n
endpoint 1 to 14
52 to 5F
read 1 byte[2]
Validate Control OUT Buffer
Validate Control IN Buffer
illegal: IN endpoints only[3]
buffer memory endpoint 0 IN[3]
(60)
-
-
-
61
Validate Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(IN endpoints only)[3]
62 to 6F
Clear Control OUT Buffer
Clear Control IN Buffer
buffer memory endpoint 0 OUT
illegal[5]
70
-
-
(71)
Clear Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(OUT endpoints only)[5]
72 to 7F
Unstall Control OUT Endpoint
Unstall Control IN Endpoint
Endpoint 0 OUT
Endpoint 0 IN
80
-
-
-
81
Unstall Endpoint n
(n = 1 to 14)
Endpoint 1 to 14
82 to 8F
Check Control OUT Status[6]
DcEndpointStatusImage register D0
endpoint 0 OUT
read 1 byte[2]
read 1 byte[2]
read 1 byte[2]
-
Check Control IN Status[6]
DcEndpointStatusImage register D1
endpoint 0 IN
Check Endpoint n Status
(n = 1 to 14)[6]
DcEndpointStatusImageregister n D2 to DF
endpoint 1 to 14
Acknowledge Set-up
Endpoint 0 IN and OUT
F4
General commands
Read Control OUT Error Code
DcErrorCode register
endpoint 0 OUT
A0
read 1 byte[2]
read 1 byte[2]
read 1 byte[2]
Read Control IN Error Code
DcErrorCode register
endpoint 0 IN
A1
Read Endpoint n Error Code
(n = 1 to 14)
DcErrorCode register
endpoint 1 to 14
A2 to AF
Unlock Device
all registers with write access
DcScratch register
B0
write 2 bytes
Write or read DcScratch register
Read Frame Number
Read Chip ID
B2/B3
B4
write or read 2 bytes
read 1 or 2 bytes
read 2 bytes
DcFrameNumber register
DcChipID register
B5
Read DcInterrupt register
DcInterrupt register
C0
read 4 bytes
[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) divided by 2.
[2] When accessing an 8-bit register in the 16-bit mode, the upper byte is invalid.
[3] Validating an OUT endpoint buffer causes unpredictable behavior of the DC.
[4] During the isochronous transfer in the 16-bit mode, because N ≤ 1023, the firmware must manage the upper byte.
[5] Clearing an IN endpoint buffer causes unpredictable behavior of the DC.
[6] Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
112 of 150
NXP [ NXP ]
