ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Code (Hex): C2/C3 — write or read InterruptEnable register
Transaction — write or read 4 bytes (code or data)
Table 116: DcInterruptEnable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
17
-
23
22
21
20
19
18
16
Symbol
Reset
Access
Bit
IEP14
IEP13
IEP12
0
IEP11
0
IEP10
0
IEP9
0
IEP8
0
IEP7
0
0
0
R/W
R/W
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
15
14
8
Symbol
Reset
Access
Bit
IEP6
IEP5
IEP4
0
IEP3
0
IEP2
0
IEP1
0
IEP0IN
0
IEP0OUT
0
0
0
R/W
0
R/W
R/W
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
7
6
SP_IEEOT
0
Symbol
Reset
Access
reserved
IEPSOF
0
IESOF
0
IEEOT
0
IESUSP
0
IERESM
0
IERST
0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 117: DcInterruptEnable register: bit description
Bit
Symbol
Description
31 to 24
-
reserved; must write logic 0
23 to 10
IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint.
9
8
7
6
5
4
3
2
1
0
IEP0IN
IEP0OUT
-
Logic 1 enables interrupts from the control IN endpoint.
Logic 1 enables interrupts from the control OUT endpoint.
reserved
SP_IEEOT
IEPSOF
IESOF
IEEOT
Logic 1 enables interrupt upon detection of a short packet.
Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF.
Logic 1 enables interrupt upon the SOF detection.
Logic 1 enables interrupt upon the EOT detection.
Logic 1 enables interrupt upon detection of a ‘suspend’ state.
Logic 1 enables interrupt upon detection of a ‘resume’ state.
Logic 1 enables interrupt upon detection of a bus reset.
IESUSP
IERESM
IERST
16.1.6 DcDMAConfiguration (R/W: F1H/F0H)
This command defines the DMA configuration of the DC and enables or disables
DMA transfers. The command accesses the DcDMAConfiguration register, which
consists of two bytes. The bit allocation is given in Table 118. A bus reset will clear
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write or read DMA Configuration
Transaction — write or read 2 bytes (code or data)
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
117 of 150
NXP [ NXP ]
