ISP1160
Embedded USB Host Controller
Philips Semiconductors
Table 45: HcµPInterruptEnable register: bit description
Bit
Symbol
-
Description
15 to 7
6
reserved
ClkReady
0 — power-up value
1 — enables ClkReady interrupt
0 — power-up value
5
HC
Suspended
Enable
1 — enables HC suspended interrupt. When the microprocessor
wants to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
4
OPR
0 — power-up value
Interrupt
Enable
1 — enables the 32-bit operational register’s interrupt (if the HC
requires the operational register to be updated)
3
2
-
reserved
EOT
0 — power-up value
Interrupt
Enable
1 — enables the EOT interrupt which indicates an end of a
read/write transfer
1
0
ATL
Interrupt
Enable
0 — power-up value
1 — enables ATL interrupt. The time for this interrupt depends on
the number of clock bits set for USB activities in each ms.
SOF
0 — power-up value
Interrupt
Enable
1 — enables the interrupt bit due to SOF (for the microprocessor
DMA to get ISO data from the HC by first accessing the
HcDMAConfiguration register)
10.5 HC miscellaneous registers
10.5.1 HcChipID register (R: 27H)
Read this register to get the ID of the ISP1160 silicon chip. The higher byte stands for
the product name. The lower byte indicates the revision number of the product
including engineering samples.
Code (Hex): 27 — read
Table 46: HcChipID register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
ChipID[15:8]
0
R
7
1
R
6
1
R
5
0
R
4
0
R
3
0
R
2
0
R
1
1
R
0
Symbol
Reset
Access
ChipID[7:0]
0
0
1
0
0
0
1
X[1]
R
R
R
R
R
R
R
R
[1] X is logic 0 for ISP1160BD and ISP1160BM; X is logic 1 for ISP1160BD/01 and ISP1160BM/01.
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
62 of 88
NXP [ NXP ]
