ISP1160
Embedded USB Host Controller
Philips Semiconductors
Table 58: HcReadBackITL0Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
RdITL0BufferLength[15:8]
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
Symbol
Reset
Access
RdITL0BufferLength[7:0]
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Table 59: HcReadBackITL0Length register: bit description
Bit Symbol Description
15 to 0 RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by
the microprocessor
10.6.5 HcReadBackITL1Length register (R: 2EH)
This register’s value stands for the current number of data bytes inside the ITL1 buffer
to be read back by the microprocessor. The HCD must set the HcTransferCounter
equivalent to this value before reading back the ITL1 buffer RAM.
Code (Hex): 2E — read
Table 60: HcReadBackITL1Length register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
RdITL1BufferLength[15:8]
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
Symbol
Reset
Access
RdITL1BufferLength[7:0]
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Table 61: HcReadBackITL1Length register: bit description
Bit Symbol Description
15 to 0 RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by
the microprocessor.
10.6.6 HcITLBufferPort register (R/W: 40H/C0H)
This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that
comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte
that comes from the ITL buffer RAM’s odd address.
Code (Hex): 40 — read
Code (Hex): C0 — write
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
66 of 88
NXP [ NXP ]
