NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
Table 7.
Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see
Figure 7;
unless otherwise specified.
Symbol
f
clk(max)
Parameter
maximum clock
frequency
Conditions
CP input;
see
V
DD
5V
10 V
15 V
[1]
Extrapolation formula
Min
6
15
20
Typ
13
30
40
Max
-
-
-
Unit
MHz
MHz
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
Table 8.
Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
P
D
Parameter
dynamic power
dissipation
V
DD
5V
10 V
15 V
Typical formula for P
D
(W)
P
D
= 900
f
i
+
(f
o
C
L
)
V
DD2
P
D
= 4300
f
i
+
(f
o
C
L
)
V
DD2
P
D
= 12000
f
i
+
(f
o
C
L
)
V
DD2
where:
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
11. Waveforms
V
DD
CP or PL INPUT
V
SS
V
OH
Qn OUTPUT
V
OL
V
M
t
PHL
V
Y
V
M
V
X
t
t
t
PLH
t
t
001aaj060
Fig 4.
Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times
1 / f
clk(max)
V
DD
CP INPUT
V
SS
t
su
V
DD
DS INPUT
V
SS
001aae611
V
M
t
h
t
W
V
M
Fig 5.
Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS.
HEF4021B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2013
7 of 16
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