NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
V
I
negative
pulse
0V
t
W
90 %
V
M
10 %
t
f
t
r
10 %
t
r
t
f
90 %
V
M
10 %
t
W
90 %
V
M
10 %
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90 %
V
M
V
I
positive
pulse
0V
a. Input waveform
V
DD
V
I
G
RT
V
O
DUT
CL
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b. Test circuit
Test data is given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 7.
Table 10.
V
DD
Test circuit for measuring switching times
Test data
Input
V
I
V
SS
or V
DD
t
r
, t
f
20 ns
Load
C
L
50 pF
Supply voltage
5 V to 15 V
HEF4021B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2013
9 of 16
PHILIPS [ NXP SEMICONDUCTORS ]
