NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
6. Functional description
Table 3.
Function table[1]
Number of clock Inputs
Outputs
Q5
transitions
CP
DS
PL
Q6
Q7
Serial operation
1
2
3
6
7
8
data 1
L
L
L
L
L
L
L
X
X
X
data 2
X
X
X
data 3
X
X
X
X
X
X
X
data 1
data 2
data 3
no change
X
X
data 1
data 2
no change
X
data 1
no change
Parallel operation
X
X
H
D5
D6
D7
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW to HIGH clock transition; = HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the nth CP transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
+18
10
Unit
V
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
mA
VI
0.5
-
VDD + 0.5
10
V
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+125
Tamb 40 C to +125 C
DIP16 package
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
SO16 and TSSOP16 package
per output
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
HEF4021B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2013
4 of 16
NXP [ NXP ]
