NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
Q5 to Q7
D0 to D7
V
SS
PL
CP
DS
V
DD
Pin description
Pin
2, 12, 3
7, 6, 5, 4, 13, 14,15, 1
8
9
10
11
16
Description
buffered parallel output from the last three stages
parallel data input
ground supply voltage
parallel load input
clock input (LOW-to-HIGH edge-triggered)
serial data input
supply voltage
HEF4021B_Q100
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Product data sheet
Rev. 3 — 30 August 2013
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