NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
V
DD
CP INPUT
V
M
V
SS
t
t
rec
W
V
DD
PL INPUT
V
M
V
SS
t
t
h
su
V
DD
90 %
Dn INPUT
V
M
10 %
V
SS
t
t
r
f
001aae612
Set-up times and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Fig 6.
Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL.
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF4021B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2013
8 of 16
NXP [ NXP ]
