NXP Semiconductors
HEF4021B-Q100
8-bit static shift register
10. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
98 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
88 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
78 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min Typ Max Unit
[1]
[1]
[1]
tPHL
HIGH to LOW
CP to Qn
see Figure 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125 250 ns
propagation delay
10 V
15 V
5 V
55
40
110
80
ns
ns
PL to Qn
see Figure 4
120 240 ns
10 V
15 V
5 V
55
40
115
50
40
110
80
ns
ns
tPLH
LOW to HIGH
CP to Qn
see Figure 4
230 ns
100 ns
propagation delay
10 V
15 V
5 V
80
ns
PL to Qn
see Figure 4
105 210 ns
10 V
15 V
5 V
50
40
60
30
20
100 ns
80 ns
120 ns
tt
transition time
set-up time
Qn; see Figure 4
10 V
15 V
5 V
60
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
DS to CP;
see Figure 5
+25 15
+25 10
+15 5
10 V
15 V
5 V
-
-
Dn to PL;
see Figure 6
50
30
20
40
20
15
25
10
5
-
10 V
15 V
5 V
-
-
th
hold time
DS to CP;
see Figure 5
20
10
8
-
10 V
15 V
5 V
-
-
Dn to PL;
see Figure 6
+15 10
-
10 V
15 V
5 V
15
15
70
30
24
70
30
24
50
40
35
0
-
0
-
tW
pulse width
CP = LOW;
minimum width;
see Figure 5
35
15
12
35
15
12
10
5
-
10 V
15 V
5 V
-
-
PL = HIGH;
minimum width;
see Figure 6
-
10 V
15 V
5 V
-
-
trec
recovery time
PL input;
see Figure 6
-
10 V
15 V
-
5
-
HEF4021B_Q100
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Product data sheet
Rev. 3 — 30 August 2013
6 of 16
NXP [ NXP ]
