PFS122
8bit MTP MCU with 12-bit R-Type ADC
6. IO Registers
6.1. ACC Status Flag Register (flag), IO address = 0x00
Bit Reset
R/W
-
Description
7 - 4
3
-
Reserved. Please do not use.
0
R/W
OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.
AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out
of low nibble in addition operation and the other one is borrow from the high nibble into low
nibble in subtraction operation.
2
0
R/W
C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition
operation, and the other one is borrow in subtraction operation. Carry is also affected by
shift with carry instruction.
1
0
0
0
R/W
R/W
Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;
Otherwise, it is cleared.
6.2. Stack Pointer Register (sp), IO address = 0x02
Bit Reset R/W
Description
Stack Pointer Register. Read out the current stack pointer, or write to change the stack
pointer.
7 - 0 R/W
-
6.3. Clock Mode Register (clkmd), IO address = 0x03
Bit Reset R/W
Description
System clock (CLK) selection:
Type 0, clkmd[3]=0 Type 1, clkmd[3]=1
000: IHRC÷4
001: IHRC÷2
010: reserved
011: EOSC÷4
100: EOSC÷2
101: EOSC
000: IHRC÷16
001: IHRC÷8
010: ILRC÷16 (ICE does NOT Support.)
011: IHRC÷32
7 - 5
111
R/W
100: IHRC÷64
101: EOSC÷8
110: ILRC÷4
11x: reserved.
111: ILRC (default)
4
3
1
0
R/W Internal High RC Enable. 0 / 1: disable / enable
Clock Type Select. This bit is used to select the clock type in bit [7:5].
0 / 1: Type 0 / Type 1.
R/W
R/W
Internal Low RC Enable. 0 / 1: disable / enable
If ILRC is disabled, watchdog timer is also disabled.
2
1
1
0
1
0
R/W Watch Dog Enable. 0 / 1: disable / enable
R/W Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB.
©Copyright 2020, PADAUK Technology Co. Ltd
Page 61 of 93
PDK-DS-PFS122-EN_V000-May 28, 2020
PADAUK [ PADAUK Technology ]
