OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
In this case, as long as there are no errors pending, i.e.
LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back
from LSR[7] and LSR[1], thus differentiating between an
‘address’ interrupt and receiver error or overrun interrupt in
9-bit mode. Note however that should an overrun or error
interrupt actually occur, an address character may also
reside in the FIFO. In this case, the software driver should
examine the contents of the receiver FIFO as well as
process the error.
15.10 Modem Disable Mask ‘MDM’
The MDM register is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts and control sleep operation due to individual
modem lines or the serial input line.
MDM[0]: Disable delta CTS
logic 0 ⇒ Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta CTS
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta CTS is disabled. It can not generate an
interrupt or wake up the UART.
The above facility produces an interrupt for recognizing any
‘address’ characters. Alternatively, the user can configure
OX16C950 to match the receiver data stream with up to
four programmable 9-bit characters and assert a level 5
interrupt after detecting a match. The interrupt occurs when
the character is transferred to the FIFO (See below).
MDM[1]: Disable delta DSR
logic 0 ⇒ Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DSR
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta DSR is disabled. In can not generate an
interrupt or wake up the UART.
NMR[0]: 9-bit mode enable
logic 0 ⇒
logic 1 ⇒
9-bit mode is disabled.
9-bit mode is enabled.
NMR[1]: Enable interrupt when 9th bit is set
MDM[2]: Disable Trailing edge RI
logic 0 ⇒
logic 1 ⇒
Receiver interrupt for detection of an
logic 0 ⇒ Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3].
Trailing edge RI can wake up the UART when it
is asleep under auto-sleep operation.
logic 1 ⇒ Trailing edge RI is disabled. In can not generate
an interrupt or wake up the UART.
‘address’ character (i.e. 9th bit set) is
disabled.
Receiver interrupt for detection of an
‘address’ character (i.e. 9th bit set) is
enabled and a level 1 interrupt is asserted.
MDM[3]: Disable delta DCD
Special Character Detection
logic 0 ⇒ Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DCD
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta DCD is disabled. In can not generate an
interrupt or wake up the UART.
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘address’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9th bit of these characters are
programmed in NMR[5] to NMR[2] respectively.
MDM[7:4]: Reserved
These bits must be set to ‘0000’
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
15.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
NMR[7:6]: Reserved
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
Data Sheet Revision 1.2
Page 38
OXFORD [ OXFORD SEMICONDUCTOR ]
