OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
logic 1 ⇒
RxRdy# is permanently inactive (high)
regardless of FIFO thresholds
DMA[7]: Force TxRdy Inactive
15.12 Good-data status register ‘GDS’
The GDS register is located at offset 0x10 of the ICR
Good data status is set when the following conditions are
true:
logic 0 ⇒
logic 1 ⇒
TxRdy# acts normally
TxRdy# is permanently inactive (high)
regardless of FIFO thresholds.
•
•
•
ISR reads level0 (no interrupt), level2 or 2a
(receiver data) or level3 (THR empty) interrupt.
LSR[7] is clear i.e. no parity error, framing error
or break in the FIFO.
15.14 Port Index Register ‘PIX’
The PIX register is located at offset 0x12 of the ICR. This
read-only register gives the UART index. For a single
channel device such as the OX16C950 this reads ‘0’.
LSR[1] is clear i.e. no overrun error has occurred.
GDS[0]: Good Data Status
GDS[7:1]: Reserved
15.15 Clock Alteration Register ‘CKA’
The CKA register is located at offset 0x13 of the ICR. This
register adds additional clock control mainly for
isochronous and embedded applications. The register is
effectively an enhancement to the CKS register.
This register is cleared to 0x00 after a hardware reset to
maintain compatibility with 16C550, but is unaffected by
software reset. This allows the user to select a clock mode
and then reset the channel to work-around any timing
glitches.
15.13 DMA Status Register ‘DMS’
The DMS register is located at offset 0x11 of the ICR. This
allows the TXRDY# and RXRDY# lines to be permanently
deasserted, and the current internal status to be monitored.
This mainly has applications for testing.
DMS[0]: RxRdy Status
Read Only: set when RxRdy is asserted (pin driven low).
DMS[1]: TxRdy Status
Read Only: set when TxRdy is asserted (pin driven low).
DMS[5:2] Reserved
DMS[6]: Force RxRdy Inactive
logic 0 ⇒
RxRdy# acts normally
Data Sheet Revision 1.2
Page 39
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