OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
CKS[6]: Transmitter clock source selector
logic 0 ⇒
The transmitter clock source is the output of
the baud rate generator (550 compatibility).
The transmitter uses an external clock
applied to the RI# pin.
15.8 Clock Select Register ‘CKS’
The CKS register is located at offset 0x03 of the ICR
logic 1 ⇒
This register is cleared to 0x00 after a hardware reset to
maintain compatibility with 16C550, but is unaffected by
software reset. This allows the user to select a clock
source and then reset the channel to work-around any
timing glitches.
CKS[7]: Transmitter 1x clock mode selector
logic 0 ⇒
The transmitter is in Nx clock mode as
defined in the TCR register. After
a
hardware reset the transmitter operates in
16x clock mode, i.e. 16C550 compatibility.
The transmitter is in isochronous 1x clock
mode.
CKS[1:0]: Receiver Clock Source Selector
logic [00] ⇒ The RCLK pin is selected for the receiver
clock (550 compatible mode).
logic 1 ⇒
logic [01] ⇒ The DSR# pin is selected for the receiver
clock.
15.9 Nine-bit Mode Register ‘NMR’
logic [10] ⇒ The output of baud rate generator (internal
BDOUT#) is selected for the receiver clock.
logic [11] ⇒ The transmitter clock is selected for the
receiver. This allows RI# to be used for both
transmitter and receiver.
The NMR register is located at offset 0x0D of the ICR
The OX16C950 offers 9-bit data framing for industrial multi-
drop applications. 9-bit mode is enabled by setting bit 0 of
the Nine-bit Mode Register (NMR). In 9-bit mode the data
length setting in LCR[1:0] is ignored. Furthermore as parity
is permanently disabled, the setting of LCR[5:3] is also
ignored.
CKS[2]: Disable BDOUT# pin
logic 0 ⇒
The BDOUT# pin is enabled and connected
to the output of the internal baud rate
generator which is a Nx clock used by the
UART. In 16C550 compatibility mode, the
baud rate generator produces a 16x clock
(See TCR, section 14.3).
The receiver stores the 9th bit of the received data in
LSR[2] (where parity error is stored in normal mode). Note
that OX16C950 provides a 128-deep FIFO for LSR[3:1].
The transmitter FIFO is 9-bit wide and 128 deep. The user
should write the 9th (MSB) data bit in SPR[0] first and then
write the other 8 bits to THR.
logic 1 ⇒
The BDOUT# pin is disabled and set
permanently low.
As parity mode is disabled, LSR[7] is set whenever there is
an overrun, framing error or received break condition. It is
unaffected by the contents of LSR[2] (Now the received 9th
data bit).
CKS[3]: Receiver 1x clock mode selector
logic 0 ⇒
The receiver is in Nx clock mode as defined
in the TCR register. After a hardware reset
the receiver operates in 16x clock mode, i.e.
16C550 compatibility.
In 9-bit mode, in-band flow control is disabled regardless of
the setting of EFR[3:0] and the XON1/XON2/XOFF1 and
XOFF2 registers are used for special character detection.
logic 1 ⇒
The receiver is in isochronous 1x clock
mode.
CKS[5:4]: Transmitter 1x clock or baud rate generator
output (BDOUT) on DTR# pin
logic [00] ⇒ The function of the DTR# pin is defined by
the setting of ACR[4:3].
logic [01] ⇒ The transmitter 1x clock (bit rate clock) is
asserted on the DTR# pin and the setting of
ACR[4:3] is ignored.
logic [10] ⇒ The output of baud rate generator (Nx clock)
is asserted on the DTR# pin and the setting
of ACR[4:3] is ignored.
Interrupts in 9-Bit Mode:
While IER[2] is set, upon receiving a character with status
error, a level 1 interrupt is asserted when the character and
the associated status are transferred to the FIFO.
The OX16C950 can assert an optional interrupt if a
received character has its 9th bit set. As multi-drop systems
often use the 9th bit as an address bit, the receiver is able
to generate an interrupt upon receiving an address
character. This feature is enabled by setting NMR[2]. This
will result in a level 1 interrupt being asserted when the
address character is transferred to the receiver FIFO.
logic [11] ⇒ Reserved.
Data Sheet Revision 1.2
Page 37
OXFORD [ OXFORD SEMICONDUCTOR ]
