OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
ACR[1]: Transmitter disable
ACR[5]: 950 mode trigger levels enable
logic 0 ⇒ The transmitter is enabled, transmitting any
data in the THR.
logic 1 ⇒ The transmitter is disabled. Any data in the
THR is not transmitted but is held. However,
in-band flow control characters may still be
transmitted.
logic 0 ⇒
Interrupts and flow control trigger levels are
as described in FCR register and are
compatible with 16C650/16C750 modes.
16C950 specific enhanced interrupt and flow
control trigger levels defined by RTL, TTL,
FCL and FCH are enabled.
logic 1 ⇒
Changes to this bit will only be recognised following the
completion of any data transmission pending.
ACR[6]: ICR read enable
logic 0 ⇒
logic 1 ⇒
The Line Status Register is readable.
The Indexed Control Registers are readable.
ACR[2]: Enable automatic DSR flow control
logic 0 ⇒ Normal. The state of the DSR# line does not
affect the flow control.
logic 1 ⇒ Data transmission is prevented whenever the
DSR# pin is held inactive high.
Setting this bit will map the ICR set to the LSR location for
reads. During normal operation this bit should be cleared.
ACR[7]: Additional status enable
This bit provides another automatic out-of-band flow control
facility using the DSR# line.
logic 0 ⇒
Access to the ASR, TFL and RFL registers
is disabled.
logic 1 ⇒
Access to the ASR, TFL and RFL registers
is enabled.
ACR[4:3]: DTR# line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmitter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR# pin,
otherwise the DTR# pin is defined as follows:
When ACR[7] is set, the MCR and LCR registers are no
longer readable but remain writable, and the TFL and RFL
registers replace them in the memory map for read
operations. The IER register is replaced by the ASR
register for all operations. The software driver may leave
this bit set during normal operation, since MCR, LCR and
IER do not generally need to be read.
logic [00] ⇒ DTR# is compatible with 16C450, 16C550,
16C650 and 16C750 (i.e. normal).
logic [01] ⇒ DTR# pin is used for out-of-band flow
control. It will be forced inactive high if the
Receiver FIFO Level (‘RFL’) reaches the
upper flow control threshold. DTR# line will
be re-activated when the RFL drops below
the lower threshold (see FCL & FCH).
logic [10] ⇒ DTR# pin is configured to drive the active
low enable pin of an external RS485 buffer.
In this configuration the DTR# pin will be
forced low whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is
high.
logic [11] ⇒ DTR# pin is configured to drive the active-
high enable pin of an external RS485 buffer.
In this configuration, the DTR# pin will be
forced high whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is
low.
If the user sets ACR[4], then the DTR# line is controlled by
the status of the transmitter empty bit of LCR. When
ACR[4] is set, ACR[3] is used to select active high or active
low enable signals. In half-duplex systems using RS485
protocol, this facility enables the DTR# line to directly
control the enable signal of external 3-state line driver
buffers. When the transmitter is empty the DTR# would go
inactive once the SOUT line returns to it’s idle marking
state.
Data Sheet Revision 1.2
Page 35
OXFORD [ OXFORD SEMICONDUCTOR ]
