OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
18 AC ELECTRICAL CHARACTERISTICS
18.1 5V Operation
Symbol
Parameter
Min
Max
Units
tsa
Address set-up time to IOR# or IOW# falling
Address set-up time to IOR or IOW rising
Address hold time after IOR# or IOW# rising Note1
Address hold time after IOR or IOW falling Note1
Chip select set-up time to IOR# or IOW# falling
Chip select set-up time to IOR or IOW rising
Chip select hold time after IOR# or IOW# rising Note1
Chip select hold time after IOR or IOW falling Note1
Pulse duration of IOR# or IOR
Delay between IOR# rising and IOR#/IOW# falling
Delay between IOR falling and IOR/IOW rising
Access time; Data valid after IOR# falling or IOR rising
Data bus floating after IOR# rising or IOR rising
Pulse duration of IOW# or IOW
Delay between IOW# rising and IOR# /IOW# falling
Delay between IOW falling and IOR/IOW rising
Data set-up time to IOW# rising or IOW falling
Data hold time after IOW# rising or IOW falling
Address and chip select set-up time to ADS#
rising Note2
0
ns
tha
tsc
thc
0
0
0
ns
ns
ns
ns
tr1
tr2
25
38
tacc
tdf
tw1
tw2
20
10
ns
ns
ns
ns
25
38
tsd
thd
tsac
0
3
0
ns
ns
ns
thac
Address and chip select hold time after ADS#
2
2
1
3
0
ns
rising Note2
ta1
thad
tirs
Pulse duration of ADS# Note2
ns
ns
ns
IOR#/IOW# rising or IOR/IOW falling to ADS# falling Note3
SIN set-up time to Isochronous input clock ‘Rx_Clk_In
rising Note4
tirh
tits
SIN hold time after Isochronous input clock ‘Rx_Clk_In’
rising Note4
SOUT valid after Isochronous output clock ‘Tx_Clk_Out’
falling Note4
ns
ns
4
Table 24: AC Electrical Characteristics
Note 1: tha and thc timing constrains only apply to non-multiplexed arrangement where ADS# is permanently tied low.
Note 2: ADS# signal may be tied low if address is stable during read or write cycles.
Note 3:
thad, ta1 and tsac timing constrains only apply to multiplexed arrangement where ADS# is used.
Note 4: In Isochronous mode, transmitter data is available after the falling edge of the x1 clock and the receiver data is sampled using the
rising edge of the x1 clock. The system designer is should ensure that mark-to-space ratio of the x1 clock is such that the required
set-up and hold timing constraint are met. One way of achieving this is to choose a crystal frequency which is twice the required data
rate and then divide the clock by two using the on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of
set-up and hold calculations.
Data Sheet Revision 1.2
Page 42
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