FEDL87V5002-01
OKI Semiconductor
ML87V5002
Register Descriptions
• Mode setting
SUB_ADDRESS=00h(R/W)
Timing generation of LRCKO, BCKO, and DO0 - 3 outputs, delay register mode, 8-ch/2-ch mode switching and
source selection in the 2-ch mode are performed.
Table 11 Mode Setting Register Map
DATA_BIT
Register Name
WR
BIT7
0
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
CMN_DLY
THRU
INT_EXT NOF_CH
DI_SEL
V
V
0
V
V
0
V
V
0
V
V
1
V
V
0
V
V
0
0
RD
Default Value
V = Valid Data
Table 12 Descriptions of the Mode Setting Register Functions
Register Name
Description
Specifies whether the delay value of each channel is set to an equal value or not.
0: Sets each channel to a delay value.
CMN_DLY
1: Sets each channel to the CH0 delay value.
Specifies the output mode.
1: Outputs the input signal specified by the “NOF_CH” or the “DI_SEL” at a delay time
of 0.
0: Performs normal delay processing and outputs the input signal.
THRU
* While the audio data are input to the DIx (x=0-3) pin (excluding LRCKx and BCKx
pins), the setting from normal operation to Through mode and/or from Through mode
to normal operation may results in output of the abnormal audio data from the DOx
(x=0-3) pin. Therefore, when changing the output mode using this bit, setting the input
data to all “0” is recommended.
Specifies the output timing of LRCK0 / BCK0 / DO0 - 3.
1: Internal generation timing
Outputs data at the timing specified by the TimingGenerate registers.
0: External input timing synchronization
INT_EXT
The DO0 - 3 signals are output synchronized to the LRCKIn / BCKn.
LRCKO/BCKO outputs LRCKIn / BCKIn without modification.
* When INT_EXT = “1”, set the register so that the FS generated by the TimingGenerate
register is coincident with the input FS.
Specifies the number of the delay processing channels.
1: 8-ch mode
Samples the DI0 - 3 input pins, performs delay processing for each channel, and
outputs data from the DO0 - 3 pins.
NOF_CH
0: 2-ch mode
Samples one input out of the DI0-3 pins selected by the “DI_SEL[1:0]” register,
performs delay processing of the 4 outputs, and outputs data from the DO0-3 pins
(2ch x 4 outputs).
* This setting bit is also valid in Through mode when THRU = “1”
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