FEDL87V5002-01
OKI Semiconductor
ML87V5002
• Right justified format
1/FS
LRCKI
BCKI
Lch
Rch
14 15 16
1
2
15 16
1
2
15 16
19 20
23 24
DI (16 bits)
MSB
LSB
19 20
18 19 20
1
2
1
2
DI (20 bits)
MSB
LSB
23 24
22 23 24
1
2
1
2
DI (24 bits)
MSB
LSB
• Left justified format
1/FS
LRCKI
BCKI
Lch
Rch
1
1
1
2
15 16
1
1
1
2
15 16
1
1
1
2
2
2
DI (16 bits)
DI (20 bits)
DI (24 bits)
MSB
2
LSB
19 20
LSB
2
2
19 20
MSB
2
23 24
23 24
MSB
LSB
• I2S format
1/FS
LRCKI
BCKI
Lch
Rch
1
1
1
2
15 16
LSB
1
1
1
2
2
2
15 16
1
1
1
2
2
2
DI (16 bits)
DI (20 bits)
DI (24 bits)
MSB
2
19 20
LSB
19 20
MSB
2
23 24
23 24
MSB
LSB
Notes:
1. In the I2S format, the MSB data is fixed with a delay of 1 BCK from left justify, and LRCK is inverted.
2. The data and LRCK alter on the falling edge of BCK.
3. The number of BCK pulses to LRCK requires twice the data length or more.
4. This figure shows the case where LRCK is not inverted.
Figure 13 Supported Format
15/36
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