FEDL87V5002-01
OKI Semiconductor
ML87V5002
Input and Output Data Lengths of DI0-3/DO0-3
This LSI can output data by changing the data length of input data. For instance, the LSI can output the 16-bit data
that is input as 20-bit data. When the output bit count is greater than the input bit count, the same value as MSB is
output for the lower-order bits. For instance, when the data that is input in a 16-bit length is output in a 20-bit
length, the higher-order 16 bits contain the value of the input data and ‘0’ is output in the lower-order 4 bits if MSB
is ‘0’ and ‘1’ if MSB is ‘1’. When the input bit count is greater than the output bit count, the lower-order bits are
ignored at output.
However, the data length must be equal to or less than 1/2 of the BCK clock count per LRCK. For instance, when
1 LRCK contains 40 BCKs, the data length must not exceed 20 bits. When the length exceeds 20 bits, BCK_ERR
is set during checking performed at the start of operation, the LSI does not start operation, but activates the INT
signal, and reports the occurrence of an error to the host CPU. However, when INTMASK is set (SUB:07h-bit[0]
=‘1’), the INT signal is not output.
External Synchronization Mode/Internal Generation Mode of LRCK/BCK
Two modes are available for signals LRCKO and BCKO, “external synchronous mode (including Through
mode)” and “internal generation mode”.
In external synchronous mode [INT_EXT (SUB:00h-bit[3])=‘0’ or THRU (SUB:00h-bit[4])=‘1’], BCKIx that is
selected by a combination of NOF_CH and DI_SEL is output through the BCKO pin.
For LRCKO, polarity reversal is performed by POLI, POLO, FMTI, or FMTO for LRCKIx that is selected by a
combination of NOF_CH and DI_SEL and the result is output.
LRCKO and BCKO are definitely output regardless of the status of the RUN bit when LRCKIx and BCKIx are
input.
In internal generation mode [INT_EXT (SUB:00h-bit[3])=‘1’ and THRU (SUB:00h-bit[4])=‘0’], LRCKO and
BCKO are generated from SYSCLK. As a result, a format different from that of input can be set without being
restricted by [output data length ≤ number of BCKIs in LRCK/2] in external synchronous mode.
The LRCKO period can be set in internal register LRCK_DIV (SUB:04h-bit[3:0]) and the BCKO period can be set
in internal register BCK_DIV (SUB:03h-bit[3:0]). (However, the LRCKO period that is generated by the setting
of LRCK_DIV and BCK_DIV must match the LRCKI period). In internal generation mode, LRCKO and BCKO
are not output while internal register RUN (SUB:08h-bit[7]) is set to ‘0’. For instance, when the internal
generation mode is set immediately after reset, internal register ENBL (SUB:07h-bit[7]) is set to ‘1’ and the RUN
bit is set to ‘0’ until delay operation starts. Therefore, LRCKO and BCKO are not output. When operation is
stopped due to an error detected during normal operation and the RUN bit is cleared to ‘0’, output of LRCKO and
BCKO is stopped. When output of LRCKO and BCKO is stopped due to detection of an error, abnormal LRCKO
and BCKO may be output while the operation shifts to a stop state. When the LSI stops operation by writing ‘0’ in
the ENBL bit during normal operation, audio data of ‘0’ is output for at least one period of LRCKO and then the
LSI stops the operation.
Through Mode
This LSI can output audio data by performing delay processing by setting internal register THRU
(SUB:00h-bit[4]) to ‘1’. When transition between through modes is performed by setting or resetting the THRU
bit, the relationship among DOx, LRCKO, and BCKO may collapse and abnormal LRCKO, LRCKO, and BCKO
may be output.
This mode is made available to output audio data without delay when output delay by 1 LRCK causes a problem
even if delay time = 0 is set in normal delay operation. Since polarity reversal for LRCK is performed by input and
output format registers, POLx and FMTx, set the mode according to the input/output.
SYSCLK
SYSCLK requires a frequency that is 128 times the sampling frequency and within 12 times BCK. However, since
the maximum operation frequency of this LSI is 25MHz, the frequency must not exceed the limit.
For instance, when the sampling frequency is 96 kHz, the frequency of 128 times is 12.288 MHz and the frequency
of 256 times is 24.576 MHz. Therefore, either frequency can be used.
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