FEDL87V5002-01
OKI Semiconductor
ML87V5002
• Input data format setting
SUB_ADDRESS=01h(R/W)
This register specifies the data bit length, I2S, input data formats (left justified and right justified), and the polarity
of the LRCK.
Table 14 Input Data Format Setting Register Map
DATA_BIT
Register Name
WR
BIT7
BIT6
BIT5
BIT4
POLI
BIT3
BIT2
BIT1
BIT0
FMTI
DI_LEN
V
V
0
V
V
0
V
V
0
V
V
0
V
V
0
0
0
0
RD
Default Value
Table 15 Descriptions of Input Data Format Setting Register Functions
Register Name
Description
Specifies the polarity of the LRCKI.
1: Inverted
0: Non-inverted
POL=1
POL=0
LRCKI
LRCKI
POLI
LEFT
RIGHT LEFT
RIGHT
I2S
1
0
0
0
1
1
0
1
1
1
0
0
Left justified (MSB)
Right justified (LSB)
Specifies the input format.
FMTI
[1:0]
00: Left justified (MSB)
00: Right justified (LSB)
10, 11: I2S
Specifies the input data bit length.
00: 16 bits
DI_LEN
[1:0]
01: 20 bits
10: 24 bits
11: 32 bits
* This field is not valid in Through mode.
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