FEDL87V5002-01
OKI Semiconductor
ML87V5002
• BCKO cycle setting
SUB_ADDRESS=03h(R/W)
This register specifies the cycle of BCKO which is generated internally when INT_EXT of the mode setting
register is “1”.
Table 18 BCKO Cycle Setting Register Map
DATA_BIT
Register Name
WR
BIT7
0
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BCK_DIV
V
V
0
V
V
1
V
V
0
V
V
0
0
0
0
RD
Default Value
• LRCKO Cycle Setting
SUB_ADDRESS=04h(R/W)
This register specifies the cycle of LRCKO which is generated internally when INT_EXT of the mode setting
register is “1”.
Table 19 LRCKO Cycle Setting Register Map
DATA_BIT
Register Name
WR
BIT7
0
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
LRCK_DIV
V
V
0
V
V
1
V
V
0
V
V
0
V
V
0
V
V
0
0
RD
Default Value
Note: Both of the registers BCK_DIV and LRCK_DIV should be configured. The new data is valid if the both
registers are configured. For example, when only the BCK_DIV register is to be changed, the BCK_DIV
register is first configured, then the LRCK_DIV register should be configured with the value equal to the
current value.
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