PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.3 Setting Input System Write Enable and Read Enable
This IC generates the write enable signals (IWE) for writing data in the valid area made up of the valid vertical
lines and the valid horizontal pixels defined by the input control mode settings to the write port of the frame
memory.
With the write enable, it is possible to set the starting point in the vertical and horizontal directions. This setting
makes it possible to position the areas of valid lines and valid pixels with non-standard phase Sync. signals.
This IC also generates a Read Enable (IRE) signal for Read operation to establish recursive noise reduction.
By setting PAOS (SUB:72h-bit[4]) to 1, the valid start offset, which is 2 lines at the setting of INPR=0 and 4 lines
at the setting of INPR=1, is set and the number of valid lines is reduced by 2 lines or 4 lines from the normal
condition.
Table F1-1-3(1) Valid Input Data Area (INPR=0: Interlace)
VMD
HMD
Valid lines
Valid pixels
[1]
0
[0]
0
[1]
0
[0]
0
288(286)
243(241)
288(286)
243(241)
288(286)
243(241)
720
720
768
640
768
768
0
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
Other than above
Test modes (not settable)
Table F1-1-3(2) Valid Input Data Area (INPR=1: Progressive)
VMD
HMD
Valid lines
Valid pixels
[1]
0
[0]
0
[1]
0
[0]
0
576(572)
486(482)
576(572)
486(482)
576(572)
486(482)
720
720
768
640
768
768
0
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
Other than above
Test modes (not settable)
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