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ML87V21071TB 参数 Datasheet PDF下载

ML87V21071TB图片预览
型号: ML87V21071TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100]
分类和应用: 商用集成电路
文件页数/大小: 123 页 / 812 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL87V21071-01  
OKI Semiconductor  
ML87V21071  
Setting of Input System Horizontal Valid Pixel Start Position  
The input system horizontal valid pixel start position (IHPS) is set in pixel unit with reference to the input  
system horizontal reset (IHR: internal signal), generated from IHS, by setting NPHWE[7:0]  
(SUB:45h-bit[7:0]).  
The data subsequent to IHPS is written in the data memory of valid pixels as the valid data.  
This value can be set in 255 levels of ±127 pixels with regard to the initial value (NPHWE[7:0] = 80h).  
In the ITU-R BT.656 mode, the value cannot be set. Write enable with regard to valid data is generated on the  
basis of detected SAV, EAV.  
Table F1-1-3 (5) Input System Horizontal Valid Pixel Start Position  
HMD  
VMD  
[0]  
IHPS position (Number of pixels from IHS)  
[1]  
[0]  
0
NPHWE=01h  
17 (–127 pixels)  
11 (–127 pixels)  
49 (–127 pixels)  
13 (–127 pixels)  
49 (–127 pixels)  
15 (–127 pixels)  
NPHWE=80h  
144 (default)  
138 (default)  
176 (default)  
140 (default)  
176 (default)  
142 (default)  
NHPWE=FFh  
271 (+127 pixels)  
265 (+127 pixels)  
303 (+127 pixels)  
267 (+127 pixels)  
303 (+127 pixels)  
269 (+127 pixels)  
……  
……  
……  
……  
……  
……  
……  
……  
……  
……  
……  
……  
……  
……  
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
Other than above  
Test modes (Setting inhibited)  
127 pixels  
127 pixels  
IHS  
IHPS  
640/720/768 pixels  
Valid data  
#IWE  
1 pixel  
1 pixel  
YI[7:0]  
CI[7:0]  
Figure F1-1-3 (5) Input System Horizontal Valid Pixel Start Timing  
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