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ML87V21071TB 参数 Datasheet PDF下载

ML87V21071TB图片预览
型号: ML87V21071TB
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100]
分类和应用: 商用集成电路
文件页数/大小: 123 页 / 812 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL87V21071-01  
OKI Semiconductor  
ML87V21071  
FUNCTIONAL DESCRIPTION  
1. Input/Output  
1.1 Memory Control  
The ML87V21071 accesses data to the input data frame memory by generating a line access type memory control  
signal from Sync. signals of the IVS and IHS pin inputs or the Sync. signals separated from SAV and EAV, and  
achieves noise reduction of frame/field/line adaptation recursive type.  
1.1.1 Input Control Mode Settings  
As shown in the table below, this IC offers a choice of 12 input control modes including the progressive mode by  
the INPR setting (SUB:44h-bit[7]), which can be selected by setting either the external setting pin mode (IRMON  
= 0 (SUB: 40h–bit [7]) or internal register mode (IRMON = 1).  
In ITU-R BT.656 input mode and in the mode of valid 720 pixels in the horizontal direction (HMD[1:0]=0h), the  
IC checks the mode by measuring the blanking period (between EAV and SAV) of the timing reference code of  
the input data (YI[7:0]) and automatically sets VMD[0] by setting APN656 = 1 (SUB: 41h-bit[2]).  
During APN656=1, do not set any value other than HMD[1:0]=1.  
Table F1-1-1 (1) Input Control Mode Setting Allocation 1  
VMD  
HMD  
IRMON  
[1]  
[0]  
[1]  
[0]  
MODE 0  
MODE 1  
0
1
SUB:40h-bit[1]  
SUB:40h-bit[1]  
SUB:40h-bit[3]  
SUB:40h-bit[3]  
(External pin)  
SUB:40h-bit[0]  
(External pin)  
SUB:40h-bit[2]  
Table F1-1-1 (2) Input Control Mode Setting Allocation 2  
INPR  
Mode  
0
1
Interlace (525i/625i)  
Progressive (525p/625p)  
* In progressive mode, neither 8-bit input mode nor ITU-R BT.656 input mode can be  
seected.  
Table F1-1-1 (3) Input Control Mode Settings(INPR=0: Interlace)  
VMD  
HMD  
Standard clock  
frequency fICLK  
[MHz]  
Number of  
valid lines  
Standard pixels  
per line  
Vertical mode  
Valid pixels  
[1]  
[0]  
[1]  
[0]  
0
0
0
0
1
0
0
0
0
0
0
1
625/50Hz 2:1  
525/60Hz 2:1  
625/50Hz 2:1  
288  
243  
288  
13.5/27  
13.5/27  
864  
858  
944  
720  
720  
768  
14.75/29.5  
12.272727/  
24.545454  
14.75/29.5  
14.31818/  
28.63636  
0
0
0
1
0
1
0
1
1
1
0
0
525/60Hz 2:1  
625/50Hz 2:1  
525/60Hz 2:1  
243  
288  
243  
780  
944  
910  
640  
768  
768  
Other than above  
Test modes  
The input system internal clock frequency fIICLK is as follows:  
16-bit input mode: fIICLK = fICLK  
8-bit input mode/ITU-R BT.656 mode: fIICLK = fICLK/2  
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