PEDL87V21071-01
OKI Semiconductor
ML87V21071
•
Setting of Input System Vertical Valid Line Start Position
The input system vertical valid line start position (IVPS) is set in line unit with reference to the input system
vertical reset (IVR: internal signal), generated from IVS, by setting NPVWE[4:0] (SUB:44h-bit[4:0]). Data of
valid lines is written in the memory taking the input data subsequent to IVPS as valid data.
For this value, ±7 lines (15 stages) can be set for the reference position (NPVWE[3:0]=8h) in interlace mode
(INPR=0) and in progressive mode (INPR=1), ±15 lines (31 stages) can be set for the reference position
(NPVWE[4:0]=10h).
In interlace mode, NPVWE[4] is ignored.
Table F1-1-3 (3) Input System Vertical Valid Line Start Position (INPR=0: Interlace)
VMD
IVPS position (number of IHS’s from IVR)
R656I
[1]
0
[0]
0
NPVWE=1h
13 (–7 lines)
NPVWE=8h
20 (default)
NPVWE=Fh
27 (+7 lines)
……
……
……
……
……
……
……
……
……
……
0
0
1
1
0
1
7 (–7 lines)
14 (default)
21 (+7 lines)
0
0
17 (–7 lines) (*1)
12 (–7 lines) (*1)
24 (default) (*1)
19 (default) (*1)
31 (+7 lines) (*1)
26 (+7 lines) (*1)
0
1
Other than above
*1: In the case of field B, it is +1.
Test modes (not settable)
Table F1-1-3 (4) Input System Vertical Valid Line Start Position (INPR=1: Progressive)
VMD
IVPS position (number of IHS’s from IVR)
R656I
[1]
0
[0]
0
NPVWE=1h
24 (–15 lines)
12 (–15 lines)
NPVWE=10h
49 (default)
27 (default)
NPVWE=1Fh
54 (+15 lines)
42 (+15 lines)
……
……
……
……
……
……
0
0
0
1
7 lines
7 lines
IVS
IHS
IVPS
#IVR
288/243 lines
#IWE/IRE
YI[7:0]
CI[8:0]
: Valid data
#: Internal signal
Figure F1-1-3 (3) Input System Vertical Valid Line Start Timing (INPR=0)
15 lines
15 lines
IVS
IHS
IVPS
#IVR
576/486 lines
#IWE/IRE
YI[7:0]
CI[8:0]
: Valid data
#: Internal signal
Figure F1-1-3 (4) Input System Vertical Valid Line Start Timing (INPR=1)
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