PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.2 Input System Field Detection
The IC detects the input data field from the phase of IVS and IHS and generates the input field pulse (IF) to
control the internal memory.
The field detection pulse can be selected from the IHS (IFLS = 0) or from 0.5H pulse IHALF (IFLS = 1) by setting
the I2C-bus setting register IFLS (SUB:42h-bit[3]).
In the rear edge of judgment area, since the field judgment uncertainty area contains 10 clocks of IICLK (internal
input system clock), external phase adjustment will be necessary if the phase of IVS lies in this area. (However,
there is no problem if the change of IVS and IHS is in the same phase.)
When a single field Sync. signal is input (8 fields or more) while the output is in progressive mode, the inter-frame
movement compensation stops.
The device also has the function to automatically generate a field pulse by judging a single field Sync. signal input
(continuous for more than 8 fields) with the setting of FCON (SUB:42h-bit[7]) = 1. For example, if there is only
field A input, the pulse toggled by IVS is regarded as the field pulse.
IVS
Field A detection
phase
IHS
Field A detection
phase
0.5H
pulse
#IF
Figure F1-1-2 (1) Input System Field A Detection Timing
IVS
Field B detection
phase
IHS
Field B detection
phase
0.5H
pulse
#IF
Figure F1-1-2 (2) Input System Field B Detection Timing
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