PEDL87V21071-01
OKI Semiconductor
ML87V21071
Table F1-1-1 (4) Input Control Mode Settings(INPR=1: Progressive)
VMD
HMD
Standard clock
frequency fICLK
[MHz]
Number of
valid lines
Standard pixels
per line
Vertical mode
Valid pixels
[1]
[0]
[1]
[0]
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
1
0
0
625/50Hz 1:1
525/60Hz 1:1
625/50Hz 1:1
525/60Hz 1:1
625/50Hz 1:1
525/60Hz 1:1
288
243
288
243
288
243
27
27
864
858
944
780
944
910
720
720
768
640
768
768
29.5
24.545454
29.5
28.63636
Test modes
Other than above
The input system internal clock frequency fIICLK is as follows:
16-bit input mode: fIICLK = fICLK
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