PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.4 Input System Sync. Signal Polarity Inversion Setting
Negative polarity IVS can also be supported by setting the I2C-bus setting register IVSINV (SUB:42h-bit[0]).
Moreover, with regard to field detection, setting is possible even when setting the internal IVR generation edge.
Table F1-1-4 (1) IVINV Setting
IVSINV
Recommended input IVS polarity
Positive (default)
Negative
IVR generation edge
Rising edge
Falling edge
0
1
IVSINV=0
IVS
IVSINV=1
IVS
IWE
IWE
Value set by
NPVWE[3:0]
Value set by
NPVWE[3:0]
Figure F1-1-4 (1) Support of Input System Vertical Sync. Signal Polarity Inversion
Negative polarity IHS can also be supported by setting the I2C-bus setting register IHSINV (SUB:42h-bit[1]).
Table F1-1-4 (2) IHSINV Setting
IHSINV
Input IHS polarity
Positive (default)
Negative
0
1
IHSINV=0
IHS
IHSINV=1
IHS
IWE
IWE
Value set by
NPHWE[7:0]
Value set by
NPHWE[7:0]
Figure F1-1-4 (2) Support of Input System Horizontal Sync. Signal Polarity Inversion
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