FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
AVREF
This is an output pin of an analog signal ground potential. With the output potential of about 1.4 V, insert
bypass capacitors of 2.2 to 4.7 µF (aluminum electrolysis type) and 0.1 µF (ceramic type) in parallel. AVREF
outputs 0.0 V at power down. AVREF starts being powered up after power-down reset, the system restarts
from ( PDNB = “1” and SPDN = “0”).
XI and XO
These are the master clock input pin (XI) and the crystal connection pins for the master clock (XI and XO).
Oscillation stops at power down by PDNB or software power down by SPDN. Oscillation starts after
power-down is reset and the clock is supplied to the LSI internal section after oscillation stabilization delay time
has elapsed (about 21.3 ms). Figure 10 shows a master clock input example.
CR0-B7
(SPDN)
PDNB
CR0-B7
(SPDN)
PDNB
To the internal
section
To the internal
section
XI
XO
CLKOUT
XI
XO
CLKOUT
R
Open
12.288 MHz
Crystal
Provisional
C1
C2
Crystal (12.288 MHz)
C1
C2
R
Kyocera Kinseki Corp.
HC-49/U-S [CL=12pF]
8 pF
8 pF
1 MΩ
Figure 10 Example of an Oscillation Circuit and Clock Input
CLKOUT
This is a 12.288 MHz master clock output pin. (Provided for 100-pin packages only)
Since output is disabled in the initial state, set the 12.288 MHz clock output enable control register
(CLKOUT_EN) to “1” when clock output is required.
PDNB
This is a power-down control input pin. A power-down state can be set by setting this pin to “0”. This pin
also functions as an LSI reset pin. To prevent an LSI operation error, use PDNB for the initial power-down
reset after power is applied. To put the LSI into a power-down state, fix PDNB to “0” for 250 µs or more.
LSI power-down reset can be performed by setting the software power down reset control register SPDN to “0”
→ “1” → “0”.
Power-down is released, the initial mode display register (READY) is set to “1” after 200 ms, and various
function setting modes (initial modes) are entered.
See Figure 1 for the timings of PDNB, AVREF, XO, and the initial mode.
(Note)
Turn on the power in a power-down state by PDNB.
When using the LSI by inputting a master clock to the XI pin, first maintain the power-down state (PDNB = 0)
until power is applied to the digital power supply (DVD0, 1, and 2) and the analog power supply (AVDD) (90%
or more) and the master clock is input to the XI pin, then release the power-down state (PDNB = 0 → 1) . In
this case also, fix PDNB to “0” for 250 µs or more.
22/42
OKI [ OKI ELECTRONIC COMPONETS ]
