FEDL7204-001DIGEST-01
OKI Semiconductor
ML7204-001
Transmit/Receive Buffer Interface (DMA Mode)
(AVDD = 3.0 to 3.6V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2
= 0.0 V, Ta = –20 to 60°C unless otherwise specified)
Parameter
DMARQ1B setup time
Symbol
tDR1S
tDR1RD
tDR1FD
tRAS
Condition
Min.
3
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
30
30
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
10
0
DMARQ1B output delay time
Address setup time (at Read)
Address hold time (at Read))
Address setup time (at Write)
Address hold time (at Write)
Write data setup time
Write data hold time
ACK0B setup time
ACK0B hold time
ACK1B setup time
ACK1B hold time
tRAH
tWAS
tWAH
tWDS
tWDH
tAK0S
tAK0H
tAK1S
tAK1H
tWW
tDR0S
tDR0RD
tDR0FD
tRDD
10
10
20
10
10
0
CL = 50 pF
10
10
10
3
—
—
—
3
WRB pulse width
DMARQ0B setup time
DMARQ0B output delay time
Read data output delay time
Read data output hold time
RDB pulse width
tRDH
tRW
tAD
35
10
ACKB disable time
DMARQ0B
Output
tDR0S
tDR0FD
tDR0RD
DMARQ1B
Output
tDR1S
tDR1FD
tDR1RD
A7-A0
Input
A2
A1
tWAS
tWAH
tRAS
tRAH
tRDH
tAK0H
D15-D0
Input-
D1
D2
Output
Input
output
tWDS tWDH
tRDD
ACK0B
Input
tAK0S
ACK1B
Input
tAK1S
tAK1H
tAD
WRB
Input
tRW
tWW
RDB
Input
Write timing
Read timing
Figure 8 Transmit/Receive Buffer Interface (DMA Mode)
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