PEDL60851C-02
1
Semiconductor
ML60851C
End Point 0 Receive Control Register (EP0RXCON)
Read address
Write address
E0h
—
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Configuration Bit (R)
Transfer Type
00 = Control transfer
End Point Address
Configuration Bit: The configuration bit of EP0 becomes “1” at the time of an USB bus reset. The packets sent
by the host computer to EP0 are received when this bit is “1”. This IC does not respond to
any transactions with this EP when this bit is “0”.
The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6
to D2 are fixed and other values written in them are invalid.
End Point 0 Receive Data Toggle Register (EP0RXTGL)
Read address
Write address
E1h
—
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
x
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
Data Sequence Toggle Bit (R)
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