PEDL60851C-02
1
Semiconductor
ML60851C
End Point 1 control Register (EP1CON)
Read address
Write address
E4h
64h
D7
0
D6
0
D5
0
D4
1
D3
1
D2
0
D1
x
D0
0
After a hardware reset
After a bus reset
Definition
0
0
0
1
1
0
x
0
0
0
1
1
0
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type
10 = Bulk Transfer
End point Address (R)
Transfer Direction (R/W)
0 = Receive, 1 = Transmit
Configuration Bit: The local MCU should write “1” in this bit during the status stage of control transfer when a
“Set Configuration” request is received from the host computer to make EP1 active.
When this bit is “1”, the exchange of data between the host computer and EP1 is enabled.
When this bit is “0”, this IC does not respond to any transactions with this EP.
Stall Bit:
When a data packet is received with a number of bytes more than the maximum packet size set
in the EP1 payload register, the ML60851C automatically sets this bit to “1”. It is also possible
for the local MCU to write a “1” in this bit. When this bit is “1”, the stall handshake is
automatically returned to the host computer in response to the packet transmitted by the host
computer to the end point. In addition, the packet ready status is not asserted and even the
INTR pin is not asserted.
The EP1 transfer mode is set as a bulk transfer and the end point address is 1h. Therefore, the bits D6 to D2 have
fixed values, and other values written in them are ignored.
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