PEDL60851C-02
1
Semiconductor
ML60851C
End Point 0 Transmit Control Register (EP0TXCON)
Read address
Write address
F0h
—
D7
0
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
Configuration Bit (R)
Transfer Type
00 = Control transfer
FIFO Number
Configuration Bit: The configuration bit of EP0 becomes “1” during an USB bus reset (both D+ and D- being “0”
for more than 2.5µs). Packets can be sent from this end point to the host computer when this bit
is “1”. This IC does not respond to any transactions with this EP when this bit is “0”.
The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6
to D2 are fixed and other values written in them are invalid.
End Point 0 Transmit Data Toggle Register (EP0TXTGL)
Read address
Write address
F1h
—
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
x
After a hardware reset
After a bus reset
Definition
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
Data Sequence Toggle Bit (R)
The synchronization based on the data sequence toggling mechanism is carried out automatically by the
ML60851C.
36/67
OKI [ OKI ELECTRONIC COMPONETS ]
