PEDL60851C-02
1
Semiconductor
ML60851C
EP2 Packet Ready Interrupt Status: When bit D2 of the interrupt enable register (INTENBL) is “1”, the negation
of bit D2 or bit D6 of the end point packet ready register (PKTRDY) is copied here. This bit
is “0” when bit D2 of INTENBL is “0”. The value at the time of a bus reset is determined
based on the value of INTENBL and the EP transfer direction at that time, and also based on
the value of the packet ready bit for that EP.
(If the EP2 transfer direction has been set as “Receive”, the negation of D2 is stored here, and
the negation of D6 is stored if the transfer direction is has been set as “Transmit”.)
During data reception, the packet ready interrupt is generated when one packet of receive
data is correctly stored in the FIFO of EP2. During transmission, the packet ready interrupt is
generated when data transmission has been completed from (and writing becomes possible
again) the FIFO of EP2.
EP0 Receive Packet Ready Interrupt Status: When bit D3 of the interrupt enable register (INTENBL) is “1”, the
content of bit D0 of the end point packet ready register (PKTRDY) is copied here. This bit is
“0” when bit D3 of INTENBL is “0”.
In other words, when one data packet is received in the data stage of control transfer and is
correctly stored in the EP0RXFIFO, this bit is set to “1” and the INTR pin is asserted.
EP0 Transmit Packet Ready Interrupt Status: When bit D4 of the interrupt enable register (INTENBL) is “1”, the
negation of the content of bit D4 of the end point packet ready register (PKTRDY) is copied
here. This bit is “0” when bit D4 of INTENBL is “0”. The value at the time of a bus reset is
determined based on the value of INTENBL and the EP transfer direction at that time, and
also based on the value of the packet ready bit of that EP.
In other words, when the transmission from the EP0RXFIFO is completed (and writing is
possible again in the FIFO) in the data stage of control transfer, this bit is set to “1” and the
INTR pin is asserted.
USB Bus Reset Interrupt Status: When bit D5 of the interrupt enable register (INTENBL) is “1”, this bit becomes
“1” during a bus reset. This bit is “0” when bit D5 of INTENBL is “0”. The value at the time
of a bus reset is determined based on the value of INTENBL and the EP transfer direction at
that time, and also based on the value of the packet ready bit of that EP.
Write a “1” in bit D5 of the device status register to return this bit to “0”.
Suspend State Interrupt Status: When bit D6 of the interrupt enable register (INTENBL) is “1”, the content of bit
D3 of the device state register (DVCSTAT) is copied here. This bit is “0” when bit D6 of
INTENBL is “0”.
EP3 Packet Ready Interrupt Status: When bit D7 of the interrupt enable register (INTENBL) is “1”, the negation
of bit D7 of the end point packet ready register (PKTRDY) is copied here. This bit is “0”
when bit D7 of INTENBL is “0”. The value at the time of a bus reset will be determined
based on the value of INTENBL and the EP transfer direction at that time, and also based on
the value of the packet ready bit of that EP.
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