PEDL60851C-02
1
Semiconductor
ML60851C
DMA Control Register (DMACON)
Read address
Write address
DDh
5Dh
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
The previous value is retained
0
0
DMA Enable
0 = DMA Inhibited
1 = DMA Transfer of EP1 is
enabled
DMA Address Mode
0 = Single address mode
1 = Dual address mode
Byte Count
0 = The byte count is not inserted.
1 = The byte count data is inserted in the
leading byte or the leading word of the
transfer data. (Note 1)
DMA Transfer Data Width
0 = Byte wide (8 bits)
1 = Word wide (16 bits) (Note 2)
DMA Transfer Mode
0 = Single transfer mode
1 = Demand transfer mode
Halting DMA Transfer
0 = Normal operation
1 = The DREQ pin is deasserted.
Note 1: In the 16-bit mode, the upper byte of the leading word is 00h.
Note 2: The allocation is made in the little-endian sequence of the upper byte followed by the LSB. In
other words, the lower byte corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15.
In the 16-bit mode, when the packet size is an odd number of bytes, the upper byte of the last
word is 00h.
Note 3: Make sure that all bits other than D7, that is, bits D4 to D0, are set completely during initialization
(at the latest, before the token packet for EP1 arrives) and are not modified thereafter.
When wanting to temporarily halt the DMA transfer in the middle, write a “1” in D7. When the
transfer is restarted by writing a “0” in D7, it is possible to restart the transfer from the byte (or
word) next to the one a the time the transfer was halted.
Note 4: The bits D6 and D5 are fixed at “0”. Even if a “1” is written in them, it will be invalid.
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