PEDL60851C-02
1
Semiconductor
ML60851C
DMA Interval Register (DMAINTVL)
Read address
Write address
DEh
5Eh
D7
0
D6
0
D5
D4
0
D3
0
D2
0
D1
0
D0
0
After a hardware reset
After a bus reset
Definition
0
The previous value is retained
Interval time
This register is used for specifying the interval of the single DMA transfer mode, that is, the interval from the
completion of the previous byte (or word) DMA transfer until DREQ is asserted again. The time per bit is 84ns
(12MHz, one period).
Interval time = (DREQ enable time) + 84 x n (ns)
See DMA timings (1), (2), (5), and (6) for details of the DREQ enable time.
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