PEDL60851C-02
1
Semiconductor
ML60851C
Interrupt Enable Register (INTENBL)
Read address
Write address
DBh
5Bh
D7
0
D6
0
D5
D4
0
D3
0
D2
0
D1
0
D0
1
After a hardware reset
After a bus reset
Definition
0
The previous value is retained
Setup ready Interrupt Enable
EP1
EP2
EP0
EP0
Packet Ready
Interrupt Enable
Packet Ready
Interrupt Enable
Receive Packet
Ready Interrupt Enable
Transmit Packet
Ready Interrupt Enable
USB Bus Reset Interrupt Enable
Suspend State Interrupt Enable
EP3 Packet Ready Interrupt Enable
The interrupts that can be accepted are set in this register. It is possible to change the setting of interrupt enable or
disable dynamically depending on the operating conditions. There is a correspondence between this register the
interrupt status register described next in terms of the bit numbers and the corresponding interrupt factors.
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