■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Configuration Register Byte 5, AR = 0005h
DR_0
[3:0]
4
C
Definition
[43:40]
44
Master PLL Reference Select [3:0]
Reserved
[6:5]
7
[46:45]
47
Master PLL Reference Frequency [1:0]
Reserved
Master PLL Reference Select [3:0] (C_ [43:40]) (Read/Write)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
ah
bh
ch
dh
eh
fh
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
None (Default)
Reserved
Reserved
Reserved
Reserved
Reserved
CT_NETREF_1
CT_NETREF_2
L_NETREF_0
L_NETREF_1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Master PLL Reference Frequency [1:0] (C_ [46:45]) (Read/Write)
00
01
10
11
→
→
→
→
8 kHz (Default)
1.536 MHz
1.544 MHz
2.048 MHz
22
Oki Semiconductor