––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 2, AR = 0002h
DR_0
C
Definition
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
Master CT Enable
Master CT A/B Select
Reserved
Advance Master PLL Timing
Master Manual/Auto Mode
Master Primary/Secondary Select
Master Primary/Secondary Read-back
Reserved
Master CT Enable (C_ [16]) (Read/Write)
Enables the Master PLL to drive the CT Bus.
0
1
→
→
Master Disabled (Default)
Master Enabled
[1]
Master CT A/B Select (C_ [17]) (Read/Write)
Selects the signal set driven by the Master PLL.
0
1
→
→
CT_C8_A & CT_FRAME_A (Default)
CT_C8_B & CT_FRAME_B
1. When in Secondary Master mode, the signal set (A or B) NOT selected here is used as the reference.
Advance Master PLL Timing (C_ [19]) (Read/Write)
When operating as secondary master, the master PLL timing may be advanced one 7.6 ns clock period to compensate for delay.
Set to 0 for normal operation.
0
1
→
→
Advance Master PLL Timing Disabled (Default)
Advance Master PLL Timing Enabled
[1]
Master Manual/Auto Mode (C_ [20]) (Read/Write)
0
1
→
→
Master Manual Mode (Default)
Master Auto Mode
1. Master Auto mode allows Secondary Master to become Primary if an error occurs on the reference signal set. To switch back to Secondary Master
it is necessary to go into manual mode.
Master Primary/Secondary Select (C_ [21]) (Read/Write)
0
1
→
→
Primary Master Select (Default)
Secondary Master Select
Master Primary/Secondary Read-back (C_ [22]) (Read Only)
0
1
→
→
Primary Master Selected
Secondary Master Selected
Oki Semiconductor
19
OKI [ OKI ELECTRONIC COMPONETS ]
