■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Configuration Register Byte 3, AR = 0003h
DR_0
C
[25:24]
26
Definition
[1:0]
SCbus SCLK Frequency [1:0]
SCbus Master Enable - SCLK, SCLKX2 & FR_COMP
Reserved
2
3
4
5
6
7
27
28
MVIP-90 Master Enable - C2, C4 & FR_COMP
H-MVIP Master Enable - C2, C4, C16 & FR_COMP
Reserved
29
30
31
Reserved
SCbus SCLK Frequency [1:0] (C_ [25:24]) (Read/Write)
00
01
10
11
→
→
→
→
2.048 MHz (Default)
4.096 MHz
8.192 MHz
Reserved
SCbus Master Enable (C_ [26]) (Read/Write)
When enabled as Primary Master, this register enables the SCLK, SCLKX2 & FR_COMP signals to be driven.
0
1
→
→
SCbus Master Disabled (Default)
SCbus Master Enabled
MVIP-90 Master Enable (C_ [28]) (Read/Write)
When enabled as Primary Master, this register enables the C2, C4 & FR_COMP signals to be driven.
0
1
→
→
MVIP-90 Master Disabled (Default)
MVIP-90 Master Enabled
H-MVIP Master Enable (C_ [29]) (Read/Write)
When enabled as Primary Master, this register enables the C2, C4, C16 & FR_COMP signals to be driven.
0
1
→
→
H-MVIP Master Disabled (Default)
H-MVIP Master Enabled
20
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
